1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques on the basis of stressed dielectric layers formed above the transistors and used for generating a strain in channel regions of the transistors.
2. Description of the Related Art
Integrated circuits typically include a very large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies for advanced semiconductor devices are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For instance, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure. The dielectric layer stack typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings connecting to the gate and drain and source terminals. Therefore, an effective control of the mechanical stress in the channel regions, i.e., an effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the associated channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher of compressive stress and up to 1 GPa and significantly higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent efficient parameters that may be used for obtaining the desired intrinsic stress.
Forming one or more stress-inducing dielectric materials above the basic transistor configurations may, therefore, represent a promising technique for further enhancing performance of transistors, wherein the degree of performance gains may significantly depend on the internal stress level of the dielectric materials and the amount of stressed material that may be positioned close to the channel region of the transistors. For this reason, deposition recipes have been developed which may enable the deposition of stressed silicon nitride materials with an internal stress level in the above-indicated range, wherein additionally, the layer thickness of the silicon nitride materials may be selected as thick as possible in order to obtain a maximum stress transfer for a given achievable internal stress level. It turns out, however, that, in extremely scaled semiconductor devices, additional device failures may occur during the formation of the critical contact level on the basis of stressed silicon nitride materials, as will be described in more detail with reference to FIG. 1a. 
FIG. 1a schematically illustrates a top view of a semiconductor device 100 which may represent any advanced semiconductor device including highly scaled transistor elements, such as transistors 150A, 150B. For example, the circuit portion illustrated in FIG. 1a may represent a portion of a RAM (random access memory) region in which, typically, a plurality of transistors are closely packed so as to provide a high bit density. The semiconductor device 100 may comprise an appropriate substrate (not shown) above which are provided semiconductor regions 103A, 103B, which may be considered as “active” regions so as to form therein transistor elements, such as the transistors 150A, 150B. Furthermore, the active regions 103A, 103B may be embedded and may thus be laterally separated by an appropriate isolation structure 102, which is typically provided in the form of a shallow trench isolation in advanced applications. The transistors 150A, 150B comprise gate electrodes 151A, 151B, respectively, which may be formed above the corresponding active regions 103A, 103B and which may extend into a neighboring active region in order to provide an efficient interconnect structure between the individual circuit elements of the semiconductor device 100. For example, the gate electrode structure 151B may be formed above the active region 103B and may also extend along the isolation structure 102 into the active region 103A so as to enable a contact of the gate electrode structure 151B with the transistor 150A via a corresponding contact element 160A. Similarly, the gate electrode structure 151A of the transistor 150A may be formed above the active region 103A and may extend along the isolation structure 102 into the active region 103B, in which a contact element 160B may connect the gate electrode structure 151A with the transistor 150B.
The semiconductor device 100 as illustrated in FIG. 1a is typically formed on the basis of the following processes. First, the isolation structure 102 may be formed, for instance, by sophisticated lithography techniques for providing an etch mask in order to determine the position and lateral size of corresponding trenches that may be formed in the semiconductor material. Thereafter, the trenches may be etched into the semiconductor material and may be subsequently filled with any appropriate dielectric material, such as silicon dioxide and the like, thereby defining the position and size of the active regions 103A, 103B. Next, the basic doping of the active regions 103A, 103B may be generated, for instance, by implantation processes using an appropriate masking regime in order to selectively introduce a required dopant species into the active regions 103A, 103B. In the example shown in FIG. 1a, it may be assumed that the active regions 103A, 103B may represent active regions for P-channel transistors and may therefore be exposed during a corresponding implantation process for incorporating an N-type dopant species, while other active regions (not shown) of N-channel transistors are masked, for instance, by a resist material. Next, the gate electrode structures 151A, 151B are provided by forming an appropriate gate dielectric material, such as a silicon dioxide-based material, a high-k dielectric material, which is to be understood as a dielectric material having a dielectric constant of approximately 10.0 or higher, and the like. It should be appreciated that, in sophisticated semiconductor devices, typically, a length of the gate electrode structures 151A, 151B may be in the range of approximately 50 nm and less, thereby requiring extremely thin silicon dioxide-based gate dielectric material which may result in a significant leakage current. For this reason, increasingly, silicon dioxide-based materials may be replaced, at least partially, by a high-k dielectric material, which may provide a superior capacitive coupling, however, at a significantly high physical thickness, thereby reducing the gate leakage currents. After the formation of the gate dielectric material, one or more appropriate electrode materials are deposited on the basis of any appropriate deposition technique. For instance, silicon may typically be used as an electrode material, possibly in combination with additional cap materials and the like, as are required for the patterning of the layer stack and the further processing of the device 100. In other cases, in addition to silicon-based material, or alternatively, other electrode materials, such as metal-containing materials and the like, may be used for enhancing overall conductivity of the gate electrode structures 151A, 151B. The patterning of the layer stack typically requires highly sophisticated lithography techniques in combination with specific etch recipes in order to obtain a desired gate length in accordance with the design rules.
Thereafter, drain and source regions 152 are formed in the active regions 103A, 103B on the basis of implantation processes, possibly in combination with other techniques, such as the incorporation of an in situ doped semiconductor material in corresponding cavities, which may be provided laterally adjacent to the gate electrode structures 151A, 151B according to some conventional process strategies. Since complex lateral dopant profiles are typically required, a sidewall spacer structure 153, indicated as dashed lines, is formed on sidewalls of the gate electrode structures 151A, 151B, thereby defining a desired lateral offset of at least a portion of the drain and source regions 152 during a corresponding implantation sequence. The spacer structure 153 is typically formed by using thermally activated chemical vapor deposition (CVD) techniques, plasma enhanced CVD techniques and the like, in combination with anisotropic etch processes. That is, a conformal spacer material in the form of a silicon nitride material is deposited and is then anisotropically etched, wherein, due to the topography of the gate electrode structures 151A, 151B, material remains at sidewalls of the gate structures 151A, 151B after the end of the anisotropic etch process. Thereafter, deep drain and source areas of the drain and source regions 152 may be formed on the basis of implantation processes using the gate electrode structures 151A, 151B and the spacer structure 153 as an efficient implantation mask. Subsequently, anneal processes are performed in order to activate the dopant species and re-crystallize implantation-induced damage. Next, typically, a silicidation process is performed in which a refractory metal, such as nickel, platinum, cobalt and the like, is deposited and is heat treated so as to react with the crystalline silicon material in the active regions 103B, 103A, thereby forming a metal silicide that exhibits a significantly lower sheet resistivity compared to the doped drain and source regions 152. During the corresponding silicidation process, the spacer structure 153 also provides a corresponding offset of metal silicide regions (not shown) with respect to the gate electrode structures 151A, 151B since metal silicide may not be formed on dielectric surface areas, such as the spacer structure 153 and the isolation structure 102.
Consequently, the spacer structure 153 may have a significant influence on the overall performance of the resulting transistors 150A, 150B since the lateral dopant profile and the overall sheet resistivity of the drain and source regions 152 may be affected by the spacer structure 153. For this reason, deposition recipes are typically used in which a substantially conformal deposition behavior with the required material characteristics may be accomplished at an acceptable cycle time. That is, due to economic constraints, the profit-ability of semiconductor facilities may not only depend on the overall production yield, i.e., the ratio of good products to non-acceptable products, but also on a short cycle time, which may be accomplished by maintaining the number of individual process steps at an acceptable level and by reducing the cycle time of individual processes. For this reason, frequently, deposition processes may be performed in a “pipelined” manner in which two or more deposition chambers may be sequentially passed so as to obtain the desired layer thickness without requiring undue transport capabilities for transferring a substrate from one process chamber to the next one. By performing a deposition process on the basis of a plurality of sequentially performed process steps, the overall cycle time may be reduced, while the transport resources may also be significantly less compared to the provision of the same number of process chambers operated in a parallel manner. Thus, the silicon nitride spacer material for the structure 153 is frequently deposited on the basis of multiple deposition steps, each resulting in a sub-layer of the same thickness. Moreover, forming a plurality of sub-layers of the same thickness may result in superior process control, thereby contributing to increased process uniformity for forming the spacer structure 153. Enhanced uniformity of the spacer structure 153 may directly translate into enhanced uniformity of the drain and source regions 152 and the corresponding metal silicide areas.
After completing the basic transistor configuration, i.e., after forming the metal silicide regions at least in the drain and source regions 152, a stress-inducing dielectric material, such as a silicon nitride material, is typically deposited, for instance in the form of a highly compressively stressed silicon nitride material, above the transistors 150A, 150B when representing P-channel transistors. During the deposition process, the layer thickness and thus the amount of highly stressed dielectric material is substantially determined by the distance 153D of the spacer structures 153, since selecting a thickness that is greater than half of the distance 153D may result in a significant void generation between the spacer structures 153. Consequently, an appropriate layer thickness is selected on the basis of overall configuration of the device 100 in order to provide one or more stressed dielectric materials. For example, a tensile stressed dielectric material may be positioned above N-channel transistors while a compressive stressed dielectric material may be positioned above the transistors 150A, 150B, wherein any appropriate patterning strategy may be applied. Thereafter, a further interlayer dielectric material, such as silicon dioxide and the like, may be deposited and may be planarized. The interlayer dielectric material in combination with the stress-inducing dielectric silicon nitride material may then be patterned so as to obtain corresponding openings which may then be filled with an appropriate metal, such as tungsten, possibly in combination with appropriate barrier materials, thereby forming the contact elements 106A, 106B.
After the above-described process sequence, it turns out, however, that, in particular in sophisticated device geometries, i.e., in semiconductor devices having a gate length in the above-specified range and in densely packed device areas, a significant yield loss may occur which may frequently be caused by leakage current paths or even short circuits 104, which may connect the contact elements 106A, 106B across the isolation structure 102. Consequently, densely packed device regions may be extremely failure prone, thereby contributing to a significantly reduced production yield for sophisticated semiconductor devices. For this reason, significant efforts are made in order to avoid deposition-related irregularities during the formation of stress-inducing materials in sophisticated semiconductor devices, thereby contributing to additional process complexity.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.